![]() ![]() Possible shakeouts/convergence is needed to move things forward. The major difference between them is that CXL is a master-slave architecture where the CPU is in charge, and the other devices are all subservient, while CCIX allows peer-to-peer connections with no CPU. The CXL specification’s founding promoter members included: Alibaba Group, Cisco Systems, Dell EMC, Facebook, Google, Hewlett Packard Enterprise, Huawei, Intel, and Microsoft.īoth CXL and CCIX target the same problem. So to accelerate next-generation data center performance. When the second core attempts to read that value from its cache, it won’t have the most recent version unless its cache entry is invalidated. ![]() For example, imagine a dual-core processor where each core brought a block of memory into its private cache, and then one core writes a value to a specific location. Since each core has its cache, the copy of the data in that cache may not always be the most up-to-date version. Cache coherence refers to keeping the data in these caches consistent. Why is cache coherency required?įor higher performance in a multiprocessor system, each processor usually has its cache. Hence sharing memory with a cache brings a formidable technical challenge known as coherency, which is addressed by the compute express link (CXL). The growing trend towards heterogeneous computing in the data center means that, increasingly, different processors and co-processors must work together efficiently, while sharing memory and utilizing caches for data sharing. We’re still waiting for CXL 2.0 products, but demos at the recent FMS show indicate they are getting close.The massive growth in the production and consumption of data, particularly unstructured data, like images, digitized speech, and video, results in an enormous increase in accelerators’ usage. With CPUs, GPUs, FPGAs, and network ports all being pooled, entire data centers might be made to behave like a sinlge system.īut let’s not get ahead of ourselves. For exaple, in-memory databases could take advantage of the memory pooling, he said.Ĭomponent pooling could help provide the resources needed for AI. So how will the application run in enterprise data centers benefit? Lender says most applications don’t need to change because CXL operates at the system level, but they will still get the benefits of CXL functionality. So this is going to become a standard feature in every new server in the next few years.” It’s not just IT guys who are embracing it. Kurt Lender, co-chair of the CXL marketing work group and a senior ecosystem manager at Intel, said, “It’s going to be basically everywhere. The 3.0 spec also provides for direct peer-to-peer communications over a switch or even across switch fabric, so two GPUs could theoretically talk to one another without using the network or getting the host CPU and memory involved. The CXL 3.0 spec, announced last week at the Flash Memory Summit (FMS), takes that disaggregation even further by allowing other parts of the architecture-processors, storage, networking, and other accelerators-to be pooled and addressed dynamically by multiple hosts and accelerators just like the memory in 2.0. Microsoft said that disaggregation via CXL can achieve a 9-10% reduction in overall need for DRAM.Įventually CXL it is expected to be an all-encompassing cache-coherent interface for connecting any number of CPUs, memory, process accelerators (notably FPGAs and GPUs), and other peripherals. CXL 2.0 could find that memory and put it to use. Of course you do have to buy the CXL module.ĬXL 2.0 supports memory pooling, which uses memory of multiple systems rather than just one. Microsoft has said that about 50% of all VMs never touch 50% of their rented memory. Yes, there is slightly lower performance and a little added latency, a small trade off to get more memory in a server without having to buy it. There’s slightly lower performance and a little added latency, but the tradeoff is that it provides more memory in a server without having to buy it. If a server needs more RAM, a CXL memory module in an empty PCIe 5.0 slot can provide it. ![]() CXL.mem: This provides a host processor with access to the memory of an attached device, covering both volatile and persistent memory architectures.ĬXL.mem is the big one, starting with CXL 1.1. ![]()
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